library verilog;
use verilog.vl_types.all;
entity main_vlg_check_tst is
    port(
        beep            : in     vl_logic;
        h_data          : in     vl_logic_vector(7 downto 0);
        m_data          : in     vl_logic_vector(7 downto 0);
        s_data          : in     vl_logic_vector(7 downto 0);
        sampler_rx      : in     vl_logic
    );
end main_vlg_check_tst;
